Semiconductor devices having crack-inhibiting structures

ABSTRACT

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 16/236,143, titled “SEMICONDUCTOR DEVICES HAVING CRACK-INHIBITING STRUCTURES,” filed Dec. 28, 2018, which is incorporated herein by reference in its entirety.

This application contains subject matter related to an U.S. patent application, titled “SEMICONDUCTOR PACKAGES HAVING CRACK-INHIBITING STRUCTURES.” The related application, of which the disclosure is incorporated by reference herein, is assigned to Micron Technology, Inc., and is identified as U.S. application Ser. No. 16/236,167, filed Dec. 28, 2018, now U.S. Pat. No. 10,784,212.

TECHNICAL FIELD

The present technology generally relates to semiconductor devices having crack-inhibiting structures, and more particularly relates to semiconductor devices having waffle metal structures formed beneath bonds pads thereof.

BACKGROUND

Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a protective covering. The semiconductor die can include functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the semiconductor die to be connected to higher level circuitry.

In some semiconductor packages, the bond pads of a semiconductor die can be electrically coupled to a substrate via a flip-chip die attach operation (e.g., a thermo-compression bonding or mass reflow operation) in which conductive pillars are formed on the bond pads and coupled to the substrate via a bond material that is disposed between the conductive pillars and the substrate. To attach the bond material to the substrate, the semiconductor package is heated above the liquidus temperature of the bond material to reflow the bond material to achieve a successful bond. However, heating the semiconductor package and/or subsequently cooling the semiconductor package can induce significant mechanical stress between the semiconductor die and the substrate due to a mismatch in the coefficients of thermal expansion of these components. Often, the stress can induce cracking of the semiconductor die near one or more of the bond pads, which can render the semiconductor package inoperable.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on illustrating clearly the principles of the present technology.

FIGS. 1A and 1B are side cross-sectional views of a semiconductor package at various stages in a method of manufacture in accordance with embodiments of the present technology.

FIG. 2A is an enlarged, side cross-sectional view of a portion of the semiconductor package shown in FIGS. 1A and 1B and having a metallization structure configured in accordance with the prior art.

FIG. 2B is a bottom cross-sectional view of the portion of the semiconductor package shown in FIG. 2A configured in accordance with the prior art.

FIG. 3A is an enlarged, side cross-sectional view of a portion of the semiconductor package shown in FIGS. 1A and 1B and having a metallization structure configured in accordance with an embodiment of the present technology.

FIGS. 3B and 3C are bottom cross-sectional views of the portion of the semiconductor package shown in FIG. 3A configured in accordance with embodiments of the present technology.

FIG. 4 is a schematic view of a system that includes a semiconductor device or package configured in accordance with embodiments of the present technology.

DETAILED DESCRIPTION

Specific details of several embodiments of semiconductor devices, and associated systems and methods, are described below. A person skilled in the relevant art will recognize that suitable stages of the methods described herein can be performed at the wafer level or at the die level. Therefore, depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated, die-level substrate. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to FIGS. 1A-4.

In several of the embodiments described below, a semiconductor device can include a semiconductor substrate including circuit elements, and a metallization structure (e.g., a back end of line (BEOL) structure) formed at least partially over the substrate. The metallization structure can include bond pads electrically coupled to the circuit elements. More particularly, the metallization structure can include one or more layers of conductive material electrically coupling the bond pads to the circuit elements and one or more layers of insulating material at least partially surrounding the conductive material. In some embodiments, the insulating material comprises a mechanically fragile material, such as a low-κ dielectric material, that can be susceptible to cracking or other mechanical and/or electrical failure due to mechanical stresses—for example, thermomechanical stresses induced by directly attaching the semiconductor device to a package substrate.

Accordingly, the metallization structure can further include crack-inhibiting structures positioned beneath some or all of the bond pads and configured to inhibit or retard the propagation of cracks through the insulating material. In some embodiments, the crack-inhibiting structures include (i) a metal lattice extending laterally between the bond pad and the substrate and (ii) barrier members extending vertically between the metal lattice and the bond pad. In some embodiments, the barrier members are metal walls. In some embodiments, the barrier members include (i) first barrier members that extend laterally in a first direction beneath the bond pad and have a first length, and (ii) second barrier members that extend laterally beneath the bond pad in a second direction and have a second length, wherein the first length is longer than the second length, and wherein the first direction is different than the second direction. The crack-inhibiting structures can reduce the likelihood of mechanical failure around the bond pads after, for example, a flip-chip die attach operation (e.g., a thermo-compression bonding (TCB) or mass reflow operation) is carried out to secure the bond pads of the semiconductor device to a package substrate.

Numerous specific details are disclosed herein to provide a thorough and enabling description of embodiments of the present technology. A person skilled in the art, however, will understand that the technology may have additional embodiments and that the technology may be practiced without several of the details of the embodiments described below with reference to FIGS. 1A-4. For example, some details of semiconductor devices and/or packages well known in the art have been omitted so as not to obscure the present technology. In general, it should be understood that various other devices and systems in addition to those specific embodiments disclosed herein may be within the scope of the present technology.

As used herein, the terms “vertical,” “lateral,” “upper,” “lower,” “above,” and “below” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation.

FIGS. 1A and 1B are side cross-sectional views of a semiconductor package 100 (“package 100”) at various stages in a method of manufacture in accordance with embodiments of the present technology. More particularly, FIGS. 1A and 1B illustrate the package 100 at the beginning and end, respectively, of a flip-chip die attach operation. Referring to FIGS. 1A and 1B together, the package 100 can include a semiconductor die 110 carried by a package substrate 102 and electrically coupled to the package substrate 102 via a plurality of interconnects 104.

In the illustrated embodiment, the semiconductor die 110 includes a semiconductor substrate 112 (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.) having a first side/surface 113 a and a second side/surface 113 b opposite the first side 113 a. The first side 113 a of the semiconductor substrate 112 can be an active side including one or more circuit elements 114 (e.g., wires, traces, interconnects, transistors, etc.; shown schematically) formed in and/or on the first side 113 a. The circuit elements 114 can include, for example, memory circuits (e.g., dynamic random memory (DRAM) or other type of memory circuits), controller circuits (e.g., DRAM controller circuits), logic circuits, and/or other circuits. In other embodiments, the semiconductor substrate 112 can be a “blank” substrate that does not include integrated circuit components and that is formed from, for example, crystalline, semi-crystalline, and/or ceramic substrate materials, such as silicon, polysilicon, aluminum oxide (Al₂O₃), sapphire, and/or other suitable materials. In the illustrated embodiment, the semiconductor die 110 further includes a metallization structure 116 formed over at least a portion of the first side 113 a of the semiconductor substrate 112. As described in greater detail below with reference to FIG. 2A, the metallization structure 116 can include one or more dielectric layers, metal layers, interconnects, vias, etc., and is configured to electrically couple the circuit elements 114 to the interconnects 104.

The package substrate 102 can include a redistribution layer, an interposer, a printed circuit board, a dielectric spacer, another semiconductor die (e.g., a logic die), or another suitable substrate. The package substrate 102 can further include electrical connectors 103 (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxies, and/or other suitable electrically conductive elements) electrically coupled to the package substrate 102 and configured to electrically couple the package 100 to external devices or circuitry (not shown).

In the illustrated embodiment, the first side 113 a of the semiconductor substrate 112 faces the package substrate 102 (e.g., in a direct chip attach (DCA) configuration). In other embodiments, the semiconductor die 110 can be arranged differently. For example, the second side 113 b of the semiconductor substrate 112 can face the package substrate 102 and the semiconductor die 110 can include one or more TSVs extending through the semiconductor substrate 112 to electrically couple the circuit elements 114 to the interconnects 104. Moreover, while only a single semiconductor die 110 is shown in FIGS. 1A and 1B, in other embodiments the package 100 can include one or more additional semiconductor dies stacked on and/or over the semiconductor die 110.

In the illustrated embodiment, individual ones of the interconnects include (i) a first conductive feature (e.g., a conductive pillar 106) electrically connected to the metallization structure 116 of the semiconductor die 110 and (ii) a bond material 108 formed between the conductive pillar 106 and the package substrate 102. In some embodiments, second conductive features (e.g., conductive pads) can be formed on the package substrate 102, and the bond material 108 can be formed between the second conductive features and the conductive pillars 106. The conductive pillars 106 can be formed of any suitably conductive material such as, for example, copper, nickel, gold, silicon, tungsten, conductive-epoxy, combinations thereof, etc., and can be formed from using an electroplating, electroless-plating, or other suitable process. In some embodiments, the interconnects 104 can also include barrier materials (not shown; e.g., nickel, nickel-based intermetallic, and/or gold) formed over end portions of the conductive pillars 106. The barrier materials can facilitate bonding and/or prevent or at least inhibit the electromigration of copper or other metals used to form the conductive pillars 106. While six interconnects 104 are illustrated in FIGS. 1A and 1B, the package 100 can include a smaller or greater number of interconnects 104. For example, the package 100 can include tens, hundreds, thousands, or more interconnects 104 arrayed between the semiconductor die 110 and the package substrate 102.

In some embodiments, the package 100 can further include an underfill or molded material formed over the package substrate 102 and/or at least partially around the semiconductor die 110. In some embodiments, the package 100 can include other components such as external heatsinks, a casing (e.g., thermally conductive casing), electromagnetic interference (EMI) shielding components, etc.

In FIG. 1A, the package 100 is illustrated at the beginning of the TCB operation, in which heating has caused the bond material 108 in the interconnects 104 to reflow and electrically connect the conductive pillars 106 to the package substrate 102. In some embodiments, the package 100 can be heated to 200° C. or greater (e.g., greater than about 217° C.) to reflow the bond material 108. During the TCB operation, a compressive force is applied to secure the interconnects 104 to the package substrate 102. In FIG. 1B, the package 100 is illustrated at the completion of the TCB operation, after the compressive force has been applied and after cooling the package 100 (e.g., to about 25° C.). By cooling the package 100 at this point, the bond material 108 can be solidified, securing the semiconductor die 110 to the package substrate 102.

As shown in FIG. 1B, one drawback with the illustrated TCB operation is that cooling of the package 100 can cause the semiconductor die 110 and the package substrate 102 to warp or bend relative to one another, which can introduce mechanical (e.g., thermomechanical) stresses into the package 100 (e.g., chip-package interaction (CPI) stresses). For example, the semiconductor die 110 can have a coefficient of thermal expansion (CTE) that is different than a CTE of the package substrate 102, and the CTE mismatch between these components can cause them to warp relative to one another during cooling and/or heating of the package 100. In some embodiments, the CTE of the semiconductor die 110 is lower than the CTE of the package substrate 102. Accordingly, as shown in FIG. 1B, the package substrate 102 can have a warped, non-planar shape after cooling. In other embodiments, the semiconductor die 110 or both the semiconductor die 110 and the package substrate 102 can have a non-planar, warped shape after cooling. As further shown in FIG. 1B, the CTE mismatch between the semiconductor die 110 and the package substrate 102 can laterally stress and bend the interconnects 104. This can cause cracks to form and propagate within the metallization structure 116, which can cause mechanical and/or electrical failures within the package 100.

More particularly, FIG. 2A is an enlarged, side cross-sectional view of a portion of the package 100 shown in FIGS. 1A and 1B configured in accordance with the prior art. As shown in FIG. 2A, the metallization structure 116 includes a plurality of conductive layers 222 (e.g., metallization layers; individually labeled as first through third conductive layers 222 a-222 c) that are at least partially surrounded by an insulating material 224. In general, the metallization structure 116 can be formed as part of a back end of line (BEOL) fabrication process as is known in the art. For example, the insulating material 224 can include a plurality of layers, and the layers of the insulating material 224 and the conductive layers 222 can be additively built (e.g., disposed) upon the active first side 113 a of the semiconductor substrate 112. The conductive layers 222 can be formed from electrically conductive materials such as, for example, copper, tungsten, aluminum, gold, titanium nitride, tantalum, etc., and can include more or fewer than the three layers illustrated in FIG. 2A (e.g., two layers, four layers, five layers, more than five layers, etc.). The conductive layers 222 are configured to couple the circuit elements 114 (FIGS. 1A and 1B) to corresponding ones of the interconnects 104. In the illustrated embodiment, for example, the third conductive layer 222 c can have a first surface 221 a (opposite a second surface 221 b) that is at least partially exposed from the insulating material 224 at an opening 226 therein, and that defines a bond pad 225 of the semiconductor die 110. The conductive pillar 106 of the illustrated one of the interconnects 104 is attached and electrically coupled to the first surface 221 a of the bond pad 225.

The insulating material 224 can comprise one or more layers of the same or different passivation, dielectric, or other suitable insulating material. For example, the insulating material 224 can comprise silicon oxide, silicon nitride, poly-silicon nitride, poly-silicon oxide, tetraethyl orthosilicate (TEOS), etc. In some embodiments, the insulating material 224 can at least partially comprise a dielectric material having a small dielectric constant relative to silicon oxide (a “low-κ dielectric material”). Such low-κ dielectric materials can include fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, organic polymeric dielectrics, silicon based polymeric dielectrics, etc. Notably, low-κ dielectric materials can increase the performance of the package 100, but can be mechanically fragile compared to conventional (e.g., higher-κ) dielectric materials.

Accordingly, the insulating material 224 can be relatively more prone to mechanical failure (e.g., cracking, delamination, etc.) due to the mechanical stresses induced by warping of the package 100 than other portions/components of the package 100. For example, as shown in FIG. 2A, the insulating material 224 can include a region 223 that is most susceptible to stress-induced mechanical failure. The region 223 (i) is directly adjacent to the bond pad 225 and (ii) extends between and electrically isolates the bond pad 225 and the second conductive layer 222 b. Therefore, the metallization structure 116 does not include any conductive structure, such as a vertically-extending via, that is electrically coupled to the bond pad 225 directly beneath the bond pad 225 (e.g., beneath the bond pad 225 between the bond pad 225 and the semiconductor substrate 112) and that may provide additional mechanical strength in the region 223.

FIG. 2B is a top cross-sectional view of the portion of the package 100 shown in FIG. 2A taken through the region 223 of the insulating material 224. The footprints of the bond pad 225 and the conductive pillar 106 are shown schematically in FIG. 2B. As shown, the conductive pillar 106 can have a generally oblong cross-sectional shape including (i) opposing first and second side portions 228 a and 228 b and (ii) opposing third and fourth side portions 229 a and 229 b. In other embodiments, the conductive pillar 106 can have other cross-sectional shapes such as, for example, rectilinear, polygonal, circular, irregular, etc. Referring to FIGS. 2A and 2B together, the conductive pillar 106 is stressed, bent, slanted, warped, etc., in a direction indicated by arrow X (e.g., in a direction generally from the first side portion 228 a toward the second side portion 228 b). Accordingly, the conductive pillar 106 can impart (i) a relatively high tensile stress on the metallization structure 116 (e.g., on the bond pad 225 and the insulating material 224) beneath the first side portion 228 a and (ii) a relatively high compressive stress beneath the second side portion 228 b.

The mechanical stresses induced by the conductive pillar 106 can causes cracks to form in the relatively mechanically weak insulating material 224 in, for example, the region 223 that is directly adjacent to the bond pad 225 and therefore subject to the greatest stresses. For example, as shown in FIGS. 2A and 2B, one or more cracks 227 can propagate through the insulating material 224. It is expected that any of the cracks 227 will generally (i) originate in the insulating material 224 at or near the first side portion 228 a (e.g., laterally outside or within the footprint of the conductive pillar 106 near the first side portion 228 a) and (ii) propagate laterally in the direction indicated by arrow X from proximate the first side portion 228 a (e.g., a region of high tensile stress) toward the second side portion 228 b (e.g., a region of high compressive stress). Moreover, it is expected that any of the cracks 227 can extend vertically toward, into, and/or past the conductive layers 222 a, b. As one of skill in the art will understand, however, the particular stresses imparted on the metallization structure 116, and the propagation pattern of any resulting cracks, will depend on the specific configurations (e.g., dimensions, shapes, material composition, etc.) of the conductive pillar 106 and the metallization structure 116. In some embodiments, for example, cracks may propagate in a direction that generally extends between the third and fourth side portions 229 a, b, and/or in a direction from the second side portion 228 b toward the first side portion 228 a. Cracking of the insulating material 224 can cause mechanical and/or electrical failure of the semiconductor die 110—rendering the package fully or partially inoperable. In some instances, for example, the conductive pillar 106 can fully or partially rip out of the metallization structure 116.

FIG. 3A is an enlarged, side cross-sectional view of a portion of the package 100 shown in FIGS. 1A and 1B and having a metallization structure 316 configured in accordance with an embodiment of the present technology. The metallization structure 316 can include features generally similar to the metallization structure 116 described in detail above with reference to FIGS. 1A-2B. For example, the metallization structure 316 includes the conductive layers 222 and the insulating material 224. Likewise, the third conductive layer 222 c is partially exposed in the opening 226 of the insulating material 224 and defines the bond pad 225. In the illustrated embodiment, however, the metallization structure 316 further includes a crack-blocking or crack-inhibiting structure 330 (“structure 330”) positioned beneath the bond pad 225 between the bond pad 225 and the semiconductor substrate 112. In the illustrated embodiment, the structure 330 includes (i) a conductive (e.g., metal) layer 332 and (ii) a plurality of barrier walls or barrier members 334. The structure 330 is configured to inhibit, block, and/or retard propagation of cracks through the insulating material 224.

FIGS. 3B and 3C are bottom cross-sectional views of the portion of the package 100 shown in FIG. 3A taken through the conductive layer 332 and the barrier members 334, respectively. The footprint of the conductive pillar 106 is shown schematically in FIGS. 3B and 3C. Moreover, the insulating material 224 is omitted in FIG. 3C for the sake of clarity.

Referring to FIGS. 3A and 3B together, the conductive layer 332 extends laterally between the semiconductor substrate 112 and the bond pad 225 and includes a first surface 335 a facing the second surface 221 b of the bond pad 225, and a second surface 335 b opposite the first surface 335 a. Therefore, in some embodiments, the conductive layer 332 is positioned beneath the bond pad 225 and generally parallel to the bond pad 225. In the illustrated embodiment, the bond pad 225 and the conductive layer 332 have substantially the same planform shape and dimensions and the bond pad 225 is superimposed over the conductive layer 332. In other embodiments, the conductive layer 332 can have a greater width than the bond pad 225 and can extend laterally beyond the bond pad 225, or the conductive layer 332 can be entirely within a footprint of (e.g., entirely beneath) the bond pad 225.

In some embodiments, the conductive layer 332 can be formed as part of the same BEOL fabrication process used to manufacture the first and second conductive layers 222. Accordingly, the conductive layer 332 can be generally similar to the conductive layers 222 and can comprise copper, tungsten, aluminum, gold, titanium nitride, tantalum, etc. In certain embodiments, the conductive layer 332 is electrically isolated from the circuit elements 114 (FIGS. 1A and 1B) of the package 100. That is, the conductive layer 332 can be formed as an “island” of conductive material that provides added mechanical strength beneath the bond pad 225 without serving any electrical routing function. Accordingly, in some embodiments, the structure 330 is not electrically coupled to any of the circuit elements 114, and the bond pad 225 can be electrically coupled to one or more of the circuit elements 114 (FIGS. 1A and 1B) via an electrical path that does not include the structure 330.

As best seen in FIG. 3B, the conductive layer 332 can have a “waffle” or “lattice” arrangement. More specifically, the conductive layer 332 can define a lattice structure including a plurality of intersecting first lanes 336 a and second lanes 336 b that define a plurality of openings 337 extending through the conductive layer 332. In some embodiments, the first lanes 336 a extend in a first direction between opposing first and second sides 338 a and 338 b of the conductive layer 332, and the second lanes 336 b extend in a second direction, different than the first direction, between opposing third and fourth sides 339 a and 339 b of the conductive layer 332. In the illustrated embodiment, the first and second lanes 336 a, b are arranged generally orthogonal to one another such that the openings 337 have a generally rectilinear (e.g., square) cross-sectional shape. In other embodiments, the conductive layer 332 can define a lattice structure having other configurations, dimensions, etc. For example, the first and second lanes 336 a, b can be obliquely angled relative to one another such that the openings 337 have a diamond or other polygonal cross-sectional shape. In other embodiments, individual ones of the first lanes 336 a can be arranged such that they are not parallel to one another, individual ones of the second lanes 336 b can be arranged such that they are not parallel to one another, etc.

As further shown in FIGS. 3A and 3B, the insulating material 224 can extend through the openings 337 in the conductive layer 332. In some embodiments, the insulating material 224 and the openings 337 comprise about 30% or less of the area and/or volume of the conductive layer 332. In some embodiments, the conductive layer 332 has a lattice arrangement due to manufacturing constraints that do not permit a solid or integral layer to be formed beneath the bond pad 225. For example, the lattice arrangement of the conductive layer 332 can enable probe testing of the bond pad 225. In other embodiments, however, the conductive layer 332 can include an integral layer or other arrangement of, for example, metal material.

Referring to FIG. 3A, the barrier members 334 extend vertically between the first surface 335 a of the conductive layer 332 and the second surface 221 b of the bond pad 225. In some embodiments, one or more of the barrier members 334 are attached to the first surface 335 a of the conductive layer 332 and/or to the second surface 221 b of the bond pad 225. In other embodiments, end portions of the barrier members 334 are positioned adjacent to the bond pad 225 and the conductive layer 332 but not connected thereto. Referring to FIG. 3C, the barrier members 334 can include a plurality of first barrier members 334 a and a plurality of second barrier members 334 b arranged over the first surface 335 a of the conductive layer 332 and spaced apart from one another. In the illustrated embodiment, the first barrier members 334 a extend laterally along the first lanes 336 a and the second barrier members 334 b extend laterally along the second lanes 336 b.

More particularly, the first barrier members 334 a can extend generally continuously along the first lanes 336 a from adjacent to the first side 338 a of the conductive layer 332 to adjacent to the second side 338 b of the conductive layer 332. The second barrier members 334 b are spaced apart along the second lanes 336 b such that they do not intersect the first barrier members 334 a (e.g., along the second lanes 336 adjacent to the intersections between the first and second lanes 336 a, b). Accordingly, the first barrier members 334 a can have a length that is greater than a length of the second barrier members 334 b. In some embodiments, the length of first barrier members 334 a is substantially equal to a width of the bond pad 225 such that the first barrier members 334 a extend laterally between opposing first and second sides of the bond pad 225. In some embodiments, the second barrier members 334 b can have a length that is substantially equal to a width of the openings 337. Moreover, in the illustrated embodiment, three first barrier members 334 a extend parallel to one another along individual ones of the first lanes 336 a, and groups of three second barrier members 334 b extend parallel to one another and are spaced apart along individual ones of the second lanes 336 b. In other embodiments, more or fewer of the barrier members 334 can be positioned along the first lanes 336 a and/or the second lanes 336 b and can have other orientations relative to one another (e.g., obliquely angled). In some embodiments, for example, the first and second barrier members 334 a, b can be interconnected to form another lattice structure.

The barrier members 334 can be formed from materials that have a greater mechanical strength than the insulating material 224. In some embodiments, for example, the barrier members 334 comprise a metal material (e.g., tungsten). Moreover, the barrier members 334 can be formed as part of or an extension of the BEOL fabrication process used to form the metallization structure 316. For example, after forming the conductive layer 332 and a layer of the insulating material 224 over the conductive layer 332, the layer of the insulating material 224 can be etched to form vias and the vias can be filled with tungsten and/or another suitable material to form the barrier members 334. More specifically, in some embodiments, the tungsten and/or other material can be plated onto the conductive layer 332 in the vias using a suitable electroplating or electroless-plating process, as is well known in the art. In some embodiments, the barrier members 334 have a rectilinear (e.g., rectangular) cross-sectional shape while, in other embodiments, the barrier members 334 can have other suitable cross-sectional shapes (e.g., circular, polygonal, irregular, etc.). In some embodiments, the barrier members 334 comprise about 20% or more (e.g., about 23%) of the volume between the bond pad 225 and the conductive layer 332.

Referring to FIGS. 3A-3C together, in operation, the structure 330 is configured to inhibit, block, and/or retard propagation of stress-induced cracks through the insulating material 224 and/or the conductive layers 222. As described in detail above with reference to FIGS. 2A and 2B, any cracks are expected to (i) originate in the insulating material 224 beneath the bond pad 225 proximate to the footprint (e.g., beneath the perimeter of) the conductive pillar 106, and (ii) propagate laterally across the footprint of the conductive pillar 106. Accordingly, the barrier members 334—which are formed of a material that is mechanically stronger than the insulating material 224—are positioned to block cracks from propagating a great distance laterally through the insulating material 224, thereby inhibiting or even preventing mechanical and/or electrical failure of the interconnect 104 and/or the metallization structure 316. For example, a crack originating at or near the perimeter of the footprint of the conductive pillar 106 and propagating laterally inward (e.g., in the direction indicated by the arrow X) will be blocked, deflected, etc., at least by the first barrier members 334 a which are arranged generally orthogonal thereto. Moreover, the conductive layer 332 can inhibit cracks from propagating vertically (e.g., in a direction toward the semiconductor substrate 112) through the insulating material 224 and/or through the first and second conductive layers 222 a, b.

Notably, in the illustrated embodiment, the longer first barrier members 334 a are arranged orthogonal to the likely direction of crack propagation indicated by the arrow X—for example, from a region of high tensile stress beneath the first side portion 228 a of the conductive pillar 106 to a region of high compressive stress beneath the second side portion 228 b of the conductive pillar 106. Accordingly, the structure 330 can include more high-strength barrier material positioned along a likely direction of crack propagation than along a less likely direction. In some embodiments, the structure 330 can include additional ones of the first barrier members 334 a and/or the first barrier members 334 a can be relatively thicker than the second barrier members 334 b to further increase the mechanical strength of the metallization structure 316 and thus further inhibit crack propagation through the insulating material 224.

Accordingly, the metallization structure 316 is expected to increase the mechanical strength of the semiconductor die 110 as compared to conventional metallization structures (e.g., FIGS. 2A and 2B) that include a weak dielectric layer beneath bond pads. The disclosed metallization structures can therefore reduce the likelihood of mechanical and/or electrical failure due to stress-induced cracking. Thus, the metallization structures of the present technology are expected to reduce yield loss during manufacturing of semiconductor packages (e.g., after a TCB bonding step, as a result of thermal cycling and/or thermal shock during package reliability tests, etc.) and to increase the reliability of semiconductor packages during operation (e.g., during power cycling during end-customer use). The metallization structures of the present technology are also expected to increase package performance by enabling the use of less mechanically strong dielectric materials (e.g., low-κ dielectric materials).

From the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the present technology. For example, in particular embodiments, the details of the crack-inhibiting structures may be different than those shown in the foregoing Figures. In some embodiments, the various embodiments may be combined to, for example, include combinations of (i) metal lattice structures having different arrangements of lanes, openings, etc., and/or (ii) barrier members having different arrangements, sizes, shapes, etc., that are formed in an insulating material beneath a bond pad. Moreover, barrier members can have various spacings and arrangements relative to a footprint of a conductive column or other conductive feature attached to the bond pad.

Any one of the semiconductor devices and/or packages having the features described above with reference to FIGS. 1A and 3A-3C can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 400 shown schematically in FIG. 4. The system 400 can include a processor 402, a memory 404 (e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices 406, and/or other subsystems or components 408. The semiconductor dies and/or packages described above with reference to FIGS. 1A and 3A-3C can be included in any of the elements shown in FIG. 4. The resulting system 400 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system 400 include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system 400 include lights, cameras, vehicles, etc. With regard to these and other example, the system 400 can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system 400 can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. Accordingly, the invention is not limited except as by the appended claims. Furthermore, certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein. 

I/We claim:
 1. A semiconductor device, comprising: a substrate; and a metallization structure over the substrate, wherein the metallization structure includes— an insulating material; a bond pad exposed from the insulating material; a metal layer extending laterally between the bond pad and the substrate, wherein the metal layer has a first side and a second side opposite the first side; and a plurality of barrier members extending (a) vertically between the metal layer and the bond pad and (b) from adjacent to the first side of the metal layer to adjacent to the second side of the metal layer.
 2. The semiconductor device of claim 1 wherein the barrier members extend continuously from adjacent to the first side of the metal layer to adjacent to the second side of the metal layer.
 3. The semiconductor device of claim 1 wherein the barrier members are first barrier members, wherein the metal layer further includes a third side opposite a fourth side, and further comprising second barrier members extending (a) vertically between the metal layer and the bond pad and (b) at least partially between the third and fourth sides of the metal layer.
 4. The semiconductor device of claim 3 wherein the first barrier members extend continuously from adjacent to the first side of the metal layer to adjacent to the second side of the metal layer.
 5. The semiconductor device of claim 4 wherein the second barrier members are interspersed between adjacent pairs of the first barrier members.
 6. The semiconductor device of claim 3 wherein the first barrier members are longer than the second barrier members in a direction extending laterally between the bond pad and the substrate.
 7. The semiconductor device of claim 1 wherein the metal layer has a lattice structure including a plurality of openings.
 8. A semiconductor device, comprising: a substrate; and a metallization structure over the substrate, wherein the metallization structure includes— an insulating material; a bond pad exposed from the insulating material; a metal layer extending laterally between the bond pad and the substrate; a plurality of first barrier members extending vertically between the metal layer and the bond pad, wherein the first barrier members have a first length in a direction extending laterally between the bond pad and the substrate; and a plurality of second barrier members extending vertically between the metal layer and the bond pad, wherein the second barrier members have a second length in the direction extending laterally between the bond pad and the substrate, wherein the second length is longer than the first length.
 9. The semiconductor device of claim 8 wherein the first barrier members extend orthogonal to the second barrier members.
 10. The semiconductor device of claim 8 wherein the first and second barrier members each have a rectangular cross-sectional shape.
 11. The semiconductor device of claim 8 wherein the first and second barrier members comprise tungsten, and wherein the metal layer comprises a material selected from the group consisting of copper and aluminum.
 12. The semiconductor device of claim 8 wherein the metal layer has a lattice structure defining a plurality of openings, and wherein the second length is substantially equal to a width of the openings.
 13. The semiconductor device of claim 12 wherein the openings have a rectilinear cross-sectional shape, and wherein the insulating material is in the openings.
 14. The semiconductor device of claim 8 wherein the first barrier members extend generally parallel to one another, and wherein the second barrier members extend generally parallel to one another.
 15. A semiconductor device, comprising: a substrate; and a metallization structure over the substrate, wherein the metallization structure includes— an insulating material; a bond pad having a first surface exposed from the insulating material and a second surface opposite the first surface; first elongate members beneath the second surface of the bond pad, wherein the first elongate members extend laterally in a first direction and have a first length; and second elongate members beneath the second surface of the bond pad, wherein the second elongate members extend laterally in a second direction and have a second length, wherein the first length is longer than the second length, and wherein the first direction is different than the second direction.
 16. The semiconductor device of claim 15 wherein the first elongate members extend continuously from adjacent a first side of the bond pad to adjacent a second side of the bond pad.
 17. The semiconductor device of claim 15 wherein the metallization structure further includes a metal lattice extending generally parallel to the second surface of the bond pad beneath the bond pad, and wherein the first and second elongate members extend generally vertically between the metal lattice and the second surface of the bond pad.
 18. The semiconductor device of claim 17 wherein the metal lattice defines a plurality of openings, and wherein the second length is substantially equal to a width of the openings.
 19. The semiconductor device of claim 15 wherein the insulating material includes a low-κ dielectric material.
 20. The semiconductor device of claim 15 wherein the first direction is generally orthogonal to the second direction, and wherein a number of the first elongate members is less than a number of the second elongate members. 